import circt.stage._

object Elaborate extends App {
  def top    = new ysyx_23060189(32, 32)
  // def alu     = new Alu(32, 32)
  // def decoder = new Decoder(32)
  // def immGen  = new ImmGen(32)
  // def pc      = new PC(32)
  // def rf      = new RegisterFile(32)

  val generator_top = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
  (new ChiselStage).execute(args, generator_top :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog))

  // val generator_alu = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => alu))
  // (new ChiselStage).execute(args, generator_alu :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog))
  //
  // val generator_decoder = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => decoder))
  // (new ChiselStage).execute(args, generator_decoder :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog))
  //
  // val generator_immGen = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => immGen))
  // (new ChiselStage).execute(args, generator_immGen :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog))
  //
  // val generator_pc = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => pc))
  // (new ChiselStage).execute(args, generator_pc :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog))
  //
  // val generator_rf = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => rf))
  // (new ChiselStage).execute(args, generator_rf :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog))
}
